1. Field of the Invention
Embodiments of the present invention relate to the field of timing controllers. More particularly, embodiments of the present invention relate generally to duty cycle control of a clock signal through a negative feedback control loop.
2. Related Art
Liquid crystal displays (LCDs) are important to the television market. However, pushing LCDs to the next generation by simply scaling existing LCD monitor panels to wider formats (e.g., 16:9 HDTV) and larger formats is a complicated endeavor. A number of television requirements push beyond conventional state-of-the art monitors. For instance, response time, brightness, contrast, color envelope, color temperature, and progressive scan-and-hold issues require a re-engineering of the monitor solution.
Specifically, LCD televisions bring forward a completely new set of challenges that are broader than simple data signaling issues. The demand for up to HDTV formats (1920×1080) on display sizes beyond 50 inches are problematic. For example, longer transmission distances (due to larger display sizes) and higher data rates (due to larger pixel formats) combine to push clock and data registration beyond stable limits.
In particular, many high speed interfaces, such as those required in displays, tightly specify the minimum and maximum duty cycle that an output clock can exhibit and still stay within specification. This duty cycle distortion can enter and accumulate anywhere along the clock path from the clock source to the output driver and anywhere in between. Examples of where duty cycle distortion can enter the system include the input buffer, on-chip clock generators such as phase-locked loops (PLLs) and oscillators, long clock buffer trees, multiplexors, the output buffer, etc.
In a chip with a high speed interface, any variation of the output clock high/low time on the order of hundreds of pico-seconds can throw an otherwise good device outside the specified range and thus lower the yield of the given product.